Imran Baig (VA), Roger Fan (Cardiology), Kaveh Sadigh (Cardiology), Edward Sun (Gastroenterology), and Lorenzo Ottaviano (Chief).įrom left: Drs. Fries!īy Department of Medicine Department of Medicine faculty and resident inducted into the Alpha Omega Alpha (AOA) Honor Medical Society.įour of our faculty and a chief resident were recognized for their contribution to medical school education by medical students and inducted into the AOA in a ceremony that took place on March 27, 2018. She has actively recruited faculty to expand Stony Brook’s reach in global health. Her laboratory is highly productive (seven publications in 2018). The other half of her group works on a highly translational research project, that is directed to the development of antibody therapeutics to multi drug resistant Klebsiella. Half of her laboratory studies the effects of replicative aging in pathogenic fungi with novel, highly innovative methods. Fries presently has two active research grants (NIH and VA Merit). The AAM is the honorific leadership group within the American Society for Microbiology (ASM), the world's oldest and largest life science organization. Over the last 50 years, over 2,500 distinguished scientists have been elected to The American Academy of Microbiology (AAM or Academy).
Ekhard Wimmer, The former Chair of Molecular Genetics and Microbiology, who is also a Fellow of that Organization, as well as a Fellow of the American Association for the Advancement of Sciences and a member of the National Academy of Sciences.
Fries was elected Fellow of the American Academy of Microbiology.
IEEE International Solid-State Circuits Conference (ISSCC), pages 430–432, Feb. A 64Gb 533Mb/s DDR interface MLC NAND Flash in sub-20nm technology. 2012.ĭaeyeal Lee, Ik Joon Chang, Sang-Yong Yoon, Joonsuc Jang, Dong-Su Jang, Wook-Ghee Hahn, Jong-Yeol Park, Doo-Gon Kim, Chiweon Yoon, Bong-Soon Lim, Byung-Jun Min, Sung-Won Yun, Ji-Sang Lee, Il-Han Park, Kyung-Ryun Kim, Jeong-Yun Yun, Youse Kim, Yong-Sung Cho, Kyung-Min Kang, Sang-Hyun Joo, Jin-Young Chun, Jung-No Im, Seunghyuk Kwon, Seokjun Ham, Ansoo Park, Jae-Duk Yu, Nam-Hee Lee, Tae-Sung Lee, Moosung Kim, Hoosung Kim, Ki-Whan Song, Byung-Gil Jeon, Kihwan Choi, Jin-Man Han, Kye Hyun Kyung, Young-Ho Lim, and Young-Hyun Jun. In IEEE International Solid-State Circuits Conference (ISSCC), pages 430–432, Feb. Go back to reference Daeyeal Lee, Ik Joon Chang, Sang-Yong Yoon, Joonsuc Jang, Dong-Su Jang, Wook-Ghee Hahn, Jong-Yeol Park, Doo-Gon Kim, Chiweon Yoon, Bong-Soon Lim, Byung-Jun Min, Sung-Won Yun, Ji-Sang Lee, Il-Han Park, Kyung-Ryun Kim, Jeong-Yun Yun, Youse Kim, Yong-Sung Cho, Kyung-Min Kang, Sang-Hyun Joo, Jin-Young Chun, Jung-No Im, Seunghyuk Kwon, Seokjun Ham, Ansoo Park, Jae-Duk Yu, Nam-Hee Lee, Tae-Sung Lee, Moosung Kim, Hoosung Kim, Ki-Whan Song, Byung-Gil Jeon, Kihwan Choi, Jin-Man Han, Kye Hyun Kyung, Young-Ho Lim, and Young-Hyun Jun. IEEE International Solid-State Circuits Conference (ISSCC), pages 422–424, Feb. A 19nm 112.8mm \(^\) 64Gb multi-level flash memory with 400Mb/s/pin 1.8V Toggle Mode interface. Go back to reference N. Shibata, K. Kanda, T. Hisada, K. Isobe, M. Sato, Y. Shimizu, T. Shimizu, T. Sugimoto, T. Kobayashi, K. Inuzuka, N. Kanagawa, Y. Kajitani, T. Ogawa, J. Nakai, K. Iwasa, M. Kojima, T. Suzuki, Y. Suzuki, S. Sakai, T. Fujimura, Y. Utsunomiya, T. Hashimoto, M. Miakashi, N. Kobayashi, M. Inagaki, Y. Matsumoto, S. Inoue, Y. Suzuki, D. He, Y. Honda, J. Musha, M. Nakagawa, M. Honma, N. Abiko, M. Koyanagi, M. Yoshihara, K. Ino, M. Noguchi, T. Kamei, Y. Kato, S. Zaitsu, H. Nasu, T. Ariki, H. Chibvongodze, M. Watanabe, H. Ding, N. Ookuma, R. Yamashita, G. Liang, G. Hemink, F. Moogat, C. Trinh, M. Higashitani, T. Pham, and K. Kanazawa. For each case, this chapter includes design examples and corresponding simulation results. number of Flash channels, number of NAND Flash memories, number of processor cores, etc.).
Of course, in all cases SSD simulations are used to identify the right architecture to achieve the design target, while minimizing the resource request (e.g. In particular, we consider 3 different cases: design for maximum bandwidth, design for minimum latency, and performance/reliability trade-off. In this chapter we describe the main actors of the drive architecture and we show how a dedicated CAD tool such as SSDExplorer can be used to optimize the SSD design, given a set of constraints. Therefore, at the beginning of the development process, a thorough design space exploration is strongly recommended. In fact, depending on the most important requirements, such as bandwidth, latency or reliability, architecture and cost of the drive might be totally different. During the design phase of an SSD, the target application must be always taken into account.
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